Flash and other types of nonvolatile electronic memory devices are constructed of memory cells operative to individually store and provide access to binary information or data in a nonvolatile memory. In typical nonvolatile memory architectures, each cell includes an MOS transistor structure having a source, a drain, and a channel in a substrate or P-well, as well as a stacked gate structure overlying the channel. The individual memory cells are organized into individually addressable units or groups such as bytes, which comprise eight cells, or words, which may include sixteen or more such cells, usually configured in multiples of eight. Storage of data in such memory device architectures is performed by writing to a particular set of memory cells, sometimes referred to as programming the cells. Retrieval of data from the cells is accomplished in a read operation. In addition to programming and read operations, groups of cells in a memory device may be erased, wherein each cell in the group is programmed to a known state. The bytes or words of memory cells are accessed for read, program, or erase operations through address decoding circuitry using conductive interconnects typically referred to as wordlines and bitlines.
Cells in flash memory devices may be interconnected in a variety of different configurations. One such configuration is the NAND configuration. Referring initially to FIGS. 1 and 2, a core region or portion of a NAND flash memory device 10 formed according to a conventional method comprises a NAND array 12. The NAND array 12 includes one or more cells 14, series connected source to drain within source/drain regions 16 along columns of conductive programming lines 18, commonly known as bitlines, as illustrated by the dashed line 60. Typically, a NAND array may comprise a series string of thirty-two (32) memory cells 14 between a select drain gate transistor 28 and a select source gate transistor 24, although for the sake of brevity, only four such memory cells are shown. Bitlines are selected by addressing select drain gate transistor 28. Individual cells 14 within an associated bitline 18 are selected via rows of wordlines 20 connected to the gate stack of each memory cell 14. The wordlines 20 along the bitline 18 control the flow of current between a source line structure 22 and a bitline contact region 32. Between the columns of bitlines 18 are regions of shallow trench isolation (STI) 30 to isolate and separate adjacent bitline active areas.
An N-channel NAND array 12 of FIGS. 1 and 2 comprises a P-type silicon substrate 40 within and over which are formed a plurality of memory cells 14. The memory cells 14 typically comprise a charge trapping layer such as in a conventional oxide-nitride-oxide (ONO) layer or stack 46 comprising, for example, a silicon nitride layer disposed between upper and lower silicon dioxide layers. A polysilicon gate 48 overlies the upper oxide layer of the ONO stack 46 and may be doped with an n-type impurity. A charge blocking layer, such as a high-dielectric constant material layer 50, may be disposed between the ONO stack 46 and the polysilicon gate 48. As used herein, the term “high dielectric constant material” means any insulating material having a dielectric constant greater than the dielectric constant of silicon dioxide. Sidewall spacers 52 are disposed about the sidewalls of the memory cells 14 as well as along the sidewalls of select drain gate transistor 28, and select source gate transistor 24 and are formed of an insulating material. Cell spacers 44 overlie sidewall spacers 52 about the sidewalls of the memory cells 14, select drain gate transistor 28, and select source gate transistor 24 and are formed of another insulative material. Source/drain regions 16, lightly doped with an n-type impurity such as phosphorus or arsenic are formed between the memory gate stacks while the bitline contact region 32 and the source line structure 22 may be typically heavily doped with an additional n-type implant 42 using sidewall spacers 52 and cell spacers 44 as an impurity doping mask.
During a READ operation of a selected cell 54, a high voltage, for example, 5 volts, is applied to the unselected wordlines, the select drain gate 28, and the select source gate 24 to turn on those transistors. A READ voltage of, for example, 1 volt is applied to the word line of the selected cell. The programmed state of the selected cell is determined by monitoring whether or not current flows along the bitline of the selected cell 54. Current will flow if the READ voltage exceeds the threshold voltage (VT) of the selected cell and will not flow if the selected cell has been programmed with a threshold voltage that is higher than the READ voltage.
As device densities increase and product dimensions decrease, it is desirable to reduce the size of the various structures and features associated with individual memory cells, sometimes referred to as scaling. However, the fabrication techniques used to produce conventional flash memory arrays limit or inhibit the designer's ability to reduce array dimensions. For example, in conventional array fabrication, implantation to fabricate the source/drain regions is performed after the layers of the gates are etched. However, as the source/drain regions become smaller in scale, short channel effects become a bigger challenge. In addition, etching of the ONO stacks of the gates may result in damage to the silicon nitride charge trapping layer of the ONO stacks, causing poor data retention or low gate-to-substrate breakdown voltage.
Accordingly, it is desirable to provide a method for fabricating a scaled flash memory device that overcomes short channel effects. In addition, it is desirable to provide a method for fabricating a flash memory device that minimizes damage to the charge trapping layer of the memory cells. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.